The present invention relates to a amplifier circuit for conducting amplification by using one or more differential amplifier circuits. Particularly this invention relates to an amplifier circuit that compensates an offset voltage caused by, for example, dispersion of transistor characteristics.
Amplifier circuits used in optical communication systems have multi-stage connected differential amplifier circuits in order to amplify a wide band signal ranging from low frequencies to high frequencies. These differential amplifier circuits are integrated in order to reduce the size and cost. In such integrated circuits, dispersion generating due to transistors cannot be neglected. In other words, a direct current component of a voltage input to a positive-phase input terminal of a differential amplifier circuit is deviated from a direct current component of a voltage input to an negative-phase input terminal due to variations of the temperature and power supply voltage, resulting in an offset voltage. This offset voltage is amplified by the multi-stage differential amplifier circuit, causing a duty variation between the positive-phase and the negative-phase. This causes a problem that a desired output amplitude cannot be obtained.
Japanese Patent Application Laid-Open No. 11-4265 discloses an amplifier that solves the above-mentioned problem. FIG. 5 is a diagram showing a configuration of this conventional amplifier. This amplifier includes a differential amplifier circuit 83, which receives an input signal fed from an input terminal 81 as a positive-phase input thereof, and which outputs a positive-phase signal and a negative-phase signal respectively to output terminals 85 and 86. Moreover, there are provided a peak detector circuit 87, which receives the negative-phase output of the differential amplifier circuit 83 as an input thereof, and a differential amplifier circuit 89, which receives an output signal of the peak detector circuit 87 as a negative-phase thereof, receives a reference voltage 90 serving as a linear operation upper limit voltage of the output signal of the differential amplifier circuit 83 as a positive-phase input thereof, and supplies an output thereof to the differential amplifier circuit 83 as its negative-phase input. The differential amplifier circuit 89 forms an offset compensation voltage generator circuit 88. The input signal supplied from the input terminal 81 is supposed to be a rectangular signal of xe2x80x9c1xe2x80x9dand xe2x80x9c0.xe2x80x9d
The differential amplifier circuit 83 amplifies the input signal fed from the input terminal 81, and outputs the positive-phase signal and the negative-phase signal to the output terminals 85 and 86, respectively. The peak detector circuit 87 is supplied with the negative-phase output signal fed from the differential amplifier circuit 83. The peak detector circuit 87 detects a peak voltage of the negative-phase output signal, which corresponds to xe2x80x9c0xe2x80x9d of the input signal. The differential amplifier circuit 89 detects an offset voltage on the basis of the reference voltage 90 serving as the linear operation upper limit voltage of the output signal and the peak voltage detected by the peak detector circuit 87, generates an offset compensation voltage by inverting the polarity of the detected offset voltage, and feeds back the generated offset compensation voltage to the differential amplifier circuit 83. As a result, the offset voltage can be automatically compensated.
By providing the offset compensation voltage generator circuit 88 with a gain, the offset voltage can be further reduced. Denoting an offset voltage generated in the output of the differential amplifier circuit 83 by VOFFOUT, an offset voltage contained in the input signal of the differential amplifier circuit 83 by VOFFIN, an offset compensation voltage fed back to the differential amplifier circuit 83 by xcex94V, and a gain of the differential amplifier circuit 83 by G1, the offset voltage VOFFOUT is represented by the following equation (1).
VOFFOUT=(VOFFINxe2x88x92xcex94V)xc2x7G1xe2x80x83xe2x80x83(1)
Denoting a detection efficiency of the peak detector circuit 87 by xcex7, and again of the offset compensation voltage generator circuit 88 by xe2x80x9cG2,xe2x80x9d the offset compensation voltage xcex94V is represented by the following equation (2).
xcex94V=VOFFOUTxc2x7xcex7xc2x7G2xe2x80x83xe2x80x83(2)
By substituting the equation (2) into the equation (1) and rewriting a resultant equation, the offset voltage VOFFOUT is represented by the following equation (3).
VOFFOUT=(G1/(1+G1xc2x7xcex7xc2x7G2))xc2x7VOFFINxe2x80x83xe2x80x83(3)
Supposing (G1xc2x7xcex7xc2x7G2) greater than  greater than 1, the equation (3) can be represented as equation (4).
VOFFOUT≈(1/(xcex7xc2x7G2))xc2x7VOFFINxe2x80x83xe2x80x83(4)
For example, in the case where xcex7=0.5 and G2=30 dB, it follows that VOFFOUT≈(1/16)xc2x7VOFFIN. The offset voltage generated in the output of the differential amplifier circuit 83 is thus reduced.
According to the above-described conventional technique, however, the offset compensation voltage generated by the offset compensation voltage generator circuit is fed back to the differential amplifier circuit as it is. This results in a problem that an excessive offset compensation voltage is fed back and consequently stable offset compensation cannot be conducted in some cases. For example, if the amplitude of the input signal exceeds the linear operation range of the differential amplifier circuit, resultant saturation of the peak detection value hinders an accurate offset compensation voltage from being generated, disadvantageously resulting in occurrence of an unstable feedback operation.
Especially, when the offset compensation voltage generation circuit is provided with a gain for reducing the offset voltage, an excessive offset compensation voltage is disadvantageously fed back for the offset voltage that has actually occurred in the output. Furthermore, if the differential amplifier circuit is an equalization amplifier circuit, a large amplitude signal input lowers the gain of the equalization amplifier circuit, and consequently the gain of the offset compensation voltage generator circuit becomes dominant in the feedback loop, and an excessive offset compensation voltage is disadvantageously fed back for the offset voltage that has actually occurred in the output.
It is an object of the present invention to provide an amplifier circuit that makes it possible to limit an excessive offset compensation voltage and conduct stable offset compensation.
The amplifier circuit according to this invention comprises a differential amplifier unit which includes one or more differential amplifier circuits; a detector unit which detects a peak value of an output voltage of the differential amplifier unit; a generator unit which generates an offset compensation voltage for offset compensation based on a detection result of the detector unit; and a limiter unit which limits the offset compensation voltage generated by the generator unit into a predetermined range and feeding back the limited offset compensation voltage to the differential amplifier unit.
According to the above-mentioned invention, the differential amplifier unit conducts amplification, and the detector unit detects a peak value of an output voltage of the differential amplifier unit. The generator unit generates an offset compensation voltage for offset compensation on the basis of a detection result of the detector unit, and the limiter unit limits the offset compensation voltage generated by the generator unit into a predetermined range and feeds back the limited offset compensation voltage to the differential amplifier unit. As a result, the offset compensation voltage fed back to the differential amplifier unit can be limited into a predetermined range.
In the above-mentioned amplifier circuit according to this invention, the limiter unit generates a bias voltage of the differential amplifier unit.
Thus, since the limiter unit generates a bias voltage of the differential amplifier unit, it becomes possible to generate the bias voltage of the differential amplifier unit in the amplifier circuit. Therefore, it becomes unnecessary to input the bias voltage of the differential amplifier unit from the outside.
In the above-mentioned amplifier circuit according to this invention, the detector unit detects the peak value and an intermediate value of the output voltage of the differential amplifier unit, generates a first reference voltage by adding a predetermined external voltage to a voltage of the intermediate value, and outputs the peak value and the first reference voltage to the generator unit, and the generator unit generates the offset compensation voltage on the basis of the peak value and the first reference voltage fed from the generator unit.
Thus, the detector unit detects the peak value and an intermediate value of the output voltage of the differential amplifier unit, generates a first reference voltage by adding a predetermined external voltage to a voltage of the intermediate value, and outputs the peak value and the first reference voltage to the generator unit, and the generator unit generates the offset compensation voltage on the basis of the peak value and the first reference voltage fed from the generator unit. As a result, a suitable first reference voltage can be generated by taking an intermediate value kept constant even if the offset of the output signal has shifted and adjusting a predetermined external voltage. The offset compensation voltage can be generated on the basis of the first reference voltage.
In the above-mentioned amplifier circuit according to this invention, the generator unit comprises a second reference voltage output unit which outputs a second reference voltage to the limiter unit, an operational amplifier having an output terminal connected to an input terminal of the offset compensation voltage of the limiter unit, a first resistor provided between a negative-phase input terminal of the operational amplifier and an output terminal of the peak value of the detector unit, a second resistor provided between a positive-phase input terminal of the operational amplifier and an output terminal of the first reference voltage of the detector unit, a third resistor provided between the negative-phase input terminal and the output terminal of the operational amplifier, and a fourth resistor between an output terminal of the second reference voltage output unit and the positive-phase input terminal of the operational amplifier.
Thus, since the generator unit comprises the second reference voltage output unit which outputs a second reference voltage to the limiter unit, the operational amplifier having an output terminal connected to an input terminal of the offset compensation voltage of the limiter unit, the first resistor provided between a negative-phase input terminal of the operational amplifier and an output terminal of the peak value of the detector unit, the second resistor provided between a positive-phase input terminal of the operational amplifier and an output terminal of the first reference voltage of the detector unit, the third resistor provided between the negative-phase input terminal and the output terminal of the operational amplifier, and the fourth resistor between an output terminal of the second reference voltage output unit and the positive-phase input terminal of the operational amplifier, the gain can be determined by using the ratio between the first resistor and the third resistor (the ratio between the second resistor and the fourth resistor).
In the above-mentioned amplifier circuit according to this invention, the limiter unit comprises a first transistor having a base connected to an output terminal of the offset compensation voltage of the generator unit and a collector connected to a negative-phase input terminal of the differential amplifier unit, a second transistor having an emitter connected to an emitter of the first transistor, a collector connected to a positive-phase input terminal of the differential amplifier unit, and a base supplied with the second reference voltage, a third transistor having a collector connected to the emitter of the first transistor and the emitter of the second transistor, and a base supplied with a voltage for adjustment, a fifth resistor provided between an emitter of the third transistor and a low potential side of a power supply, a sixth resistor having one terminal connected to the collector of the first transistor, a seventh resistor provided between the collector of the second transistor and the other terminal of the sixth resistor, and an eighth resistor provided between the other end of the sixth resistor and a high potential side of the power supply.
Thus, since the limiter unit comprises the first transistor having a base connected to an output terminal of the offset compensation voltage of the generator unit and a collector connected to a negative-phase input terminal of the differential amplifier unit, the second transistor having an emitter connected to an emitter of the first transistor, a collector connected to a positive-phase input terminal of the differential amplifier unit, and a base supplied with the second reference voltage, the third transistor having a collector connected to the emitter of the first transistor and the emitter of the second transistor, and a base supplied with a voltage for adjustment, the fifth resistor provided between an emitter of the third transistor and a low potential side of a power supply, the sixth resistor having one terminal connected to the collector of the first transistor, the seventh resistor provided between the collector of the second transistor and the other terminal of the sixth resistor, and the eighth resistor provided between the other end of the sixth resistor and a high potential side of the power supply, the offset compensation voltage can be limited into a predetermined range.
In the above-mentioned amplifier circuit according to this invention, the limiter unit comprises a first transistor having a base connected to an output terminal of the offset compensation voltage of the generator unit and a collector connected to a negative-phase input terminal of the differential amplifier unit, a second transistor having an emitter connected to an emitter of the first transistor, a collector connected to a positive-phase input terminal of the differential amplifier unit, and a base supplied with the second reference voltage, a third transistor having a collector connected to the emitter of the first transistor and the emitter of the second transistor, and a base supplied with a voltage for adjustment, a fifth resistor provided between an emitter of the third transistor and a low potential side of a power supply, a sixth resistor provided between the collector of the first transistor and a high potential side of the power supply, a seventh resistor provided between the collector of the second transistor and the high potential side of the power supply, an eighth resistor provided between the collector of the first transistor and the low potential side of the power supply, and a ninth resistor provided between the collector of the second transistor and the low potential side of the power supply.
Thus, since the limiter unit comprises a first transistor having a base connected to an output terminal of the offset compensation voltage of the generator unit and a collector connected to a negative-phase input terminal of the differential amplifier unit, a second transistor having an emitter connected to an emitter of the first transistor, a collector connected to a positive-phase input terminal of the differential amplifier unit, and a base supplied with the second reference voltage, a third transistor having a collector connected to the emitter of the first transistor and the emitter of the second transistor, and a base supplied with a voltage for adjustment, a fifth resistor provided between an emitter of the third transistor and a low potential side of a power supply, a sixth resistor provided between the collector of the first transistor and a high potential side of the power supply, a seventh resistor provided between the collector of the second transistor and the high potential side of the power supply, an eighth resistor provided between the collector of the first transistor and the low potential side of the power supply, and a ninth resistor provided between the collector of the second transistor and the low potential side of the power supply, the offset compensation voltage can be limited into a predetermined range.